To reap the benefits of increased component densities in memory chips, it is necessary to increase the packing density of the package which holds the memory chips. This is especially so with respect to the highest density, dynamic random access memory chips (DRAM's) now commercially available. DRAM chips have traditionally been packaged as single chip modules. That is, a single silicon die has been wire bonded to a lead frame containing wiring that fans out the necessary signals to and from the chip via a set of individual metal leads. Those leads are then connected to an underlying circuit board. The lead frame and silicon chip are usually encased in an epoxy block, from which the individual metal leads extend, such package generally being referred to as a wire bond package.
Once the chips have been packaged, they are subjected to a process known as burn-in, whereby they are operated for many hours at elevated temperatures and voltages. Packaged chips which survive the burn-in operation are then assembled into groups of chips which, in turn, are assembled into groups of groups, etc. Additionally, other components of the memory system such as control logic, error correction logic, etc., are added to the package. Characteristically, such packaging results in large and cumbersome systems which are not suitable for the highest performance DRAM memories.
A preferred package for DRAM memories is the TAB package (Tape-Automated-Bonding). TAB packages are inexpensive to produce, and, recently, machines have become available that automatically handle such packages. A TAB package comprises a film of an insulating material, e.g., Kapton, (a trademark of the DuPont Corporation, Wilmington, Del.) with personalized copper wiring patterns positioned either on one or both of its opposing surfaces. A memory chip (either "bare" or "encapsulated") is emplaced on a surface of the film and the chip's conductors are interconnected with pro-positioned conductive pads. Once the chip is bonded, the film is cut into sections, each section having "outerlead" bond areas that may, in turn, be interconnected with a further circuit carrier.
When DRAM circuits are packaged as single-chip modules, those modules are mounted in groups on circuit cards and then the circuit cards are placed together to make a memory system. In addition to the DRAM circuits, other components such as decoupling capacitors, control logic, error correction logic and line drivers are added to make a complete system. In general, the packaging of such systems lacks a common heat sink. Thus memory circuits that are frequently accessed in such packages become the hottest part of the system and are prone to thermal stress failure.
The prior art is replete with designs for high density packaging. Examples of some of these prior art teachings can be found in the following patents. In U.S. Pat. No. 4,730,232 to Lindberg, a pair of device-containing circuit boards are laminated to planar heat sinks, which heat sinks are mounted back-to-back and are enclosed within a pair of covers. In U.S. Pat. No. 4,122,508 to Rumbaugh, a separate heat sink is attached to each of a plurality of printed circuit boards, each heat sink having a plurality of fins integrally formed therein. When a number of these heat sinks are mounted on a face-to-face basis, continuous air circulation paths are formed that enable cooling of the attached circuit boards.
In U.S. Pat. No. 4,771,366 to Blake et al., a plurality of parallel-oriented ceramic card assemblies with interspersed cold plates are described. Each ceramic card has a number of chips mounted on both of its sides, which chips are enclosed by conductive caps that, in turn, bear upon the cold plates. In U.S. Pat. No. 4,841,355 to Parks, a high density package is shown having internal pathways for a liquid coolant flow. In U.S. Pat. No. 3,372,310 to Kantor, a high density package is shown wherein a plurality of chips are mounted on a substrate, an apertured spacer emplaced thereover, and the entire configuration is enclosed within metallic coverplates.
A number of prior art references disclose parallel-mounted circuit cards with pathways provided therebetween for cooling airflow. Such structures can be found in U.S. Pat. Nos. 4,107,760 to Zimmer; 4,674,004 to Smith et al.; 4,375,290 to Zucchi et al.; 4,291,364 to Andros et al.; 4,739,444 to Zushi et al.; and 3,671,812 to Peluso et al. Other liquid and liquid/air flow cooling systems can be found in U.S. Pat. Nos. 4,619,316 to Nakayama et al. and 4,315,300 to Parmerlee et al. Other multi-chip integrated circuit packaging configurations can be found in the following patents: U.S. Pat. No. 4,783,695 to Eichelberger et al.; U.S. Pat. No. 4,580,193 to Edwards; U.S. Pat. No. 4,549,200 to Ecker et al.; U.S. Pat. No. 4,868,634 to Ishida et al.; U.S. Pat. No. 4,831,433 to Ogura et al.; and U.S. Pat. No. 4,782,381 to Ruby et al.
The following patents describe methods for providing via-connections to opposite sides of a circuit board: U.S. Pat. No. 4,830,264 to Bitaillou et al.; U.S. Pat. No. 3,991,347 to Hollyday; U.S. Pat. No. 4,835,344 to Iyogi et al.; U.S. Pat. No. 4,838,475 to Mullins et al.; German patent DE 37 39 985 A1 to Inoue et al. and IBM Technical Disclosure Bulletin, Vol. 10, No. 7, December 1967 (Ecker) p. 943.